sky130_fd_sc_hd__clkinvlp¶
Lower power Clock tree inverter
This is a stub of cell description file
Cell name: sky130_fd_sc_hd__clkinvlp
Type: cell
Verilog name: sky130_fd_sc_hd__clkinvlp
Library: sky130_fd_sc_hd
Inputs: 1 (A)
Outputs: 1 (Y)
Lower power Clock tree inverter
This is a stub of cell description file
Cell name: sky130_fd_sc_hd__clkinvlp
Type: cell
Verilog name: sky130_fd_sc_hd__clkinvlp
Library: sky130_fd_sc_hd
Inputs: 1 (A)
Outputs: 1 (Y)