sky130_fd_sc_hd__clkinv¶
Clock tree inverter
This is a stub of cell description file
Cell name: sky130_fd_sc_hd__clkinv
Type: cell
Verilog name: sky130_fd_sc_hd__clkinv
Library: sky130_fd_sc_hd
Inputs: 1 (A)
Outputs: 1 (Y)
Clock tree inverter
This is a stub of cell description file
Cell name: sky130_fd_sc_hd__clkinv
Type: cell
Verilog name: sky130_fd_sc_hd__clkinv
Library: sky130_fd_sc_hd
Inputs: 1 (A)
Outputs: 1 (Y)