:cell:`sky130_fd_sc_hd__clkinv` =============================== **Clock tree inverter** *This is a stub of cell description file* - **Cell name**: :cell:`sky130_fd_sc_hd__clkinv` - **Type**: cell - **Verilog name**: sky130_fd_sc_hd__clkinv - **Library**: sky130_fd_sc_hd - **Inputs**: 1 (A) - **Outputs**: 1 (Y) :cell:`sky130_fd_sc_hd__clkinv` symbols --------------------------------------- .. list-table:: * - .. figure:: sky130_fd_sc_hd__clkinv.symbol.svg - - .. figure:: sky130_fd_sc_hd__clkinv.pp.symbol.svg :cell:`sky130_fd_sc_hd__clkinv` schematic ----------------------------------------- .. figure:: sky130_fd_sc_hd__clkinv.schematic.svg :align: center :cell:`sky130_fd_sc_hd__clkinv` GDSII layouts --------------------------------------------- .. figure:: sky130_fd_sc_hd__clkinv_1.svg :align: center :width: 50% sky130_fd_sc_hd__clkinv_1 .. figure:: sky130_fd_sc_hd__clkinv_16.svg :align: center :width: 50% sky130_fd_sc_hd__clkinv_16 .. figure:: sky130_fd_sc_hd__clkinv_2.svg :align: center :width: 50% sky130_fd_sc_hd__clkinv_2 .. figure:: sky130_fd_sc_hd__clkinv_4.svg :align: center :width: 50% sky130_fd_sc_hd__clkinv_4 .. figure:: sky130_fd_sc_hd__clkinv_8.svg :align: center :width: 50% sky130_fd_sc_hd__clkinv_8