sky130_fd_sc_hd__a32o

3-input AND into first input, and 2-input AND into 2nd input of 2-input OR

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hd__a32o

  • Type: cell

  • Verilog name: sky130_fd_sc_hd__a32o

  • Library: sky130_fd_sc_hd

  • Inputs: 5 (A1, A2, A3, B1, B2)

  • Outputs: 1 (X)

sky130_fd_sc_hd__a32o symbols

../../../../../_images/sky130_fd_sc_hd__a32o.symbol.svg
../../../../../_images/sky130_fd_sc_hd__a32o.pp.symbol.svg

sky130_fd_sc_hd__a32o schematic

../../../../../_images/sky130_fd_sc_hd__a32o.schematic.svg

sky130_fd_sc_hd__a32o GDSII layouts

../../../../../_images/sky130_fd_sc_hd__a32o_1.svg

sky130_fd_sc_hd__a32o_1

../../../../../_images/sky130_fd_sc_hd__a32o_2.svg

sky130_fd_sc_hd__a32o_2

../../../../../_images/sky130_fd_sc_hd__a32o_4.svg

sky130_fd_sc_hd__a32o_4