:cell:`sky130_fd_sc_hd__a32o` ============================= **3-input AND into first input, and 2-input AND into 2nd input of 2-input OR** *This is a stub of cell description file* - **Cell name**: :cell:`sky130_fd_sc_hd__a32o` - **Type**: cell - **Verilog name**: sky130_fd_sc_hd__a32o - **Library**: sky130_fd_sc_hd - **Inputs**: 5 (A1, A2, A3, B1, B2) - **Outputs**: 1 (X) :cell:`sky130_fd_sc_hd__a32o` symbols ------------------------------------- .. list-table:: * - .. figure:: sky130_fd_sc_hd__a32o.symbol.svg - - .. figure:: sky130_fd_sc_hd__a32o.pp.symbol.svg :cell:`sky130_fd_sc_hd__a32o` schematic --------------------------------------- .. figure:: sky130_fd_sc_hd__a32o.schematic.svg :align: center :cell:`sky130_fd_sc_hd__a32o` GDSII layouts ------------------------------------------- .. figure:: sky130_fd_sc_hd__a32o_1.svg :align: center :width: 50% sky130_fd_sc_hd__a32o_1 .. figure:: sky130_fd_sc_hd__a32o_2.svg :align: center :width: 50% sky130_fd_sc_hd__a32o_2 .. figure:: sky130_fd_sc_hd__a32o_4.svg :align: center :width: 50% sky130_fd_sc_hd__a32o_4