Skip to content
SkyWater SKY130 PDK
SkyWater PDK Python API
Type to start searching
google/skywater-pdk
SkyWater SKY130 PDK 0.0.0-329-gb5ff617 documentation
business
SkyWater
precision_manufacturing
Shuttle Program
chat_bubble
Chat
campaign
Announcements
mail
Mailing List
SkyWater SKY130 PDK
google/skywater-pdk
Versioning Information
Current Status
Version Number Format
Current Status
Known Issues
Documentation
PDK Contents Issues
Tooling Compatibility
Cadence Virtuoso Support
Mentor Calibre Support
Specific Libraries
sky130
_
fd
_
pr
_
base
sky130
_
fd
_
pr
_
rf
sky130
_
fd
_
pr
_
rf2
sky130
_
osu
_
sc
- SKY130 Oklahoma State University provided standard cell library
sky130
_
fd
_
sp
_
flash
- SKY130 Flash Build Space
sky130
_
fd
_
sp
_
sram
- SKY130 SRAM Build Space
sky130
_
fd
_
io
- SKY130 Foundry Provided IO Cells
sky130
_
ef
_
io
- SKY130 eFabless Provided IO Cells
Design Rule Checking
Using Mentor Calibre
Using Magic
Scripts and PDK Tooling
Design Rules
Background
Masks
Criteria & Assumptions
Process Stack Diagram
General
Minimum Critical Dimensions
Semiconductor Criteria
Basic Parameters
Junction Depths
Other Width Criteria
Punchthrough Criteria
Latch-up/ESD Criteria
Implant angles
Physical Criteria
Laser Fuse Criteria
Other criteria and parameters
Criteria for High Voltage FET
Criteria for polyimide manufacturability
Criteria for VPP capacitor
Layers Reference
Layers Definitions
Auxiliary Layers
Devices and Layout vs Schematic (LVS) Information
GDS Layers Information
Device and Layout vs. Schematic
Summary of Key Periphery Rules
Periphery Rules
(x.-)
(dnwell.-)
(nwell.-)
(pwbm.-)
(pwdem.-)
(hvtp.-)
(hvtr.-)
(lvtn.-)
(ncm.-)
(difftap.-)
(tunm.-)
(poly.-)
(rpm.-)
(varac.-)
(photo.-)
(npc.-)
(n/ psd.-)
(licon.-)
(li.-.-)
(ct.-)
(capm.-)
(vpp.-)
(m1.-)
(via.-)
(m2.-)
(via2.-)
(m3.-)
(via3.-)
(nsm.-)
(indm.-)
(m4.-)
(via4.-)
(m5.-)
(pad.-)
(rdl.-)
(mf.-)
(hvi.-)
(hvnwell.-)
(hvdifftap.-)
(hvpoly.-)
(hvntm.-)
(denmos.-)
(depmos.-)
(extd.-)
(hv.-.-)
(vhvi.-.-)
(uhvi.-.-)
(ulvt-.-)
(pwres.-.-)
(rfdiode.-.-)
WLCSP Rules
High Voltage Methodology
Failure Mechanisms in High Voltage Devices
High Voltage Implementation Methodology
Very High Voltage Methodology
Failure Mechanisms in VHV Devices
VHV Implementation Methodology
Antenna Rules
Definitions
Tables
Parasitic Layout Extraction
Resistance Rules
Resistance Values
Capacitance Rules
Capacitance Values
Basic Capacitance - Fringe Downward
Basic Capacitance - Fringe Upward
Basic Capacitance - Parallel
Discrepencies
Device Details
MiM Capacitor
Spice Model Information
Details
Varactors
Spice Model Information
Details
Vertical Parallel Plate (VPP) capacitors
Spice Model Information
Details
Diodes
Spice Model Information
Details
NMOS ESD FET
Spice Model Information
Details
5.0V/10.5V NMOS FET
Spice Model Information
Details
11V/16V NMOS FET
Spice Model Information
Details
1.8V low-VT NMOS FET
Spice Model Information
Details
1.8V NMOS FET
Spice Model Information
Details
3.0V native NMOS FET
Spice Model Information
Details
5.0V native NMOS FET
Spice Model Information
Details
20V NMOS FET
Spice Model Information
Details
20V isolated NMOS FET
Spice Model Information
Details
20V native NMOS FET
Spice Model Information
Details
20V NMOS zero-VT FET
Spice Model Information
Details
Bipolar (NPN)
Spice Model Information
Details
5.0V/10.5V PMOS FET
Spice Model Information
Details
10V/16V PMOS FET
Spice Model Information
Details
1.8V high-VT PMOS FET
Spice Model Information
Details
1.8V low-VT PMOS FET
Spice Model Information
Details
1.8V PMOS FET
Spice Model Information
Details
20V PMOS FET
Spice Model Information
Details
Bipolar (PNP)
Spice Model Information
Details
Generic Resistors
P+ poly precision resistors
Spice Model Information
Details
P- poly precision resistors
Spice Model Information
Details
SONOS cells
SRAM cells
Details
Spice Model Information
Spice Model Information
Spice Model Information
Error Messages
PDK Contents
Libraries
Library Naming
Creating New Libraries
Primitive
Libraries
Foundry
provided
Digital Standard Cell
Libraries
Foundry
provided
Digital Standard Cell
Libraries
Third party
provided
Digital Standard Cell
Libraries
Build Space
Libraries
Foundry
provided
Build Space
Libraries
IO and Periphery
Libraries
Foundry
provided
IO and Periphery
Libraries
Third party
provided
IO and Periphery
Libraries
File Types
Analog Design
With Cadence Virtuoso
With MAGIC
With Klayout
With Berkeley Analog Generator (BAG)
With FASoC
With your design flow?
Digital Design
With Cadence Innovus
With OpenROAD
With your design flow?
Simulation
With Cadence Spectre
With ngspice
With your design flow?
Physical & Design Verification
Automated Design Rule (DRC) Checking
With Mentor Calibre
With Magic
With KLayout
Layout Versus Schematic (LVS) Checking
With Mentor Calibre
With Magic
With KLayout
Parasitic Extraction (PEX)
With Mentor Calibre
With Magic
With KLayout
TODO: Calibre Decks
TODO: MAGIC Decks
Python API
skywater_pdk package
Submodules
skywater_pdk.base module
skywater_pdk.corners module
skywater_pdk.sizes module
skywater_pdk.utils module
Module contents
Previous Nomenclature
Glossary
How to Contribute
Contributor License Agreement
Code reviews
Community Guidelines
Resolve peacefully
Reporting problems
Partners
Open Source SkyWater PDK
Open Source MPW Shuttle Program
Industry partners
Academic partners
Show Source
SkyWater PDK Python API
ΒΆ
TODO: Add documentation here