sky130_fd_sc_ms__sedfxtp¶
Scan delay flop, data enable, non-inverted clock, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_ms__sedfxtp
Type: cell
Verilog name: sky130_fd_sc_ms__sedfxtp
Library: sky130_fd_sc_ms
Inputs: 5 (CLK, D, DE, SCD, SCE)
Outputs: 1 (Q)