sky130_fd_sc_ms__sdfxtp¶
Scan delay flop, non-inverted clock, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_ms__sdfxtp
Type: cell
Verilog name: sky130_fd_sc_ms__sdfxtp
Library: sky130_fd_sc_ms
Inputs: 4 (CLK, D, SCD, SCE)
Outputs: 1 (Q)