sky130_fd_sc_ms__sdfrtp¶
Scan delay flop, inverted reset, non-inverted clock, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_ms__sdfrtp
Type: cell
Verilog name: sky130_fd_sc_ms__sdfrtp
Library: sky130_fd_sc_ms
Inputs: 5 (CLK, D, SCD, SCE, RESET_B)
Outputs: 1 (Q)