sky130_fd_sc_ms__sdfbbp¶
Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs
This is a stub of cell description file
Cell name: sky130_fd_sc_ms__sdfbbp
Type: cell
Verilog name: sky130_fd_sc_ms__sdfbbp
Library: sky130_fd_sc_ms
Inputs: 6 (D, SCD, SCE, CLK, SET_B, RESET_B)
Outputs: 2 (Q, Q_N)
sky130_fd_sc_ms__sdfbbp symbols¶
 |
 |
sky130_fd_sc_ms__sdfbbp schematic¶
sky130_fd_sc_ms__sdfbbp GDSII layouts¶
sky130_fd_sc_ms__sdfbbp_1¶