sky130_fd_sc_ms__fahcin

Full adder, inverted carry in

This is a stub of cell description file

  • Cell name: sky130_fd_sc_ms__fahcin

  • Type: cell

  • Verilog name: sky130_fd_sc_ms__fahcin

  • Library: sky130_fd_sc_ms

  • Inputs: 3 (A, B, CIN)

  • Outputs: 2 (COUT, SUM)

sky130_fd_sc_ms__fahcin symbols

../../../../../_images/sky130_fd_sc_ms__fahcin.symbol.svg
../../../../../_images/sky130_fd_sc_ms__fahcin.pp.symbol.svg

sky130_fd_sc_ms__fahcin schematic

../../../../../_images/sky130_fd_sc_ms__fahcin.schematic.svg

sky130_fd_sc_ms__fahcin GDSII layouts

../../../../../_images/sky130_fd_sc_ms__fahcin_1.svg

sky130_fd_sc_ms__fahcin_1