sky130_fd_sc_ms__edfxtp

Delay flop with loopback enable, non-inverted clock, single output

This is a stub of cell description file

• Cell name: sky130_fd_sc_ms__edfxtp

• Type: cell

• Verilog name: sky130_fd_sc_ms__edfxtp

• Library: sky130_fd_sc_ms

• Inputs: 3 (CLK, D, DE)

• Outputs: 1 (Q)

sky130_fd_sc_ms__edfxtp symbols

sky130_fd_sc_ms__edfxtp schematic

sky130_fd_sc_ms__edfxtp GDSII layouts

sky130_fd_sc_ms__edfxtp_1