sky130_fd_sc_ms__dlygate4sd2¶
Delay Buffer 4-stage 0.18um length inner stage gates
This is a stub of cell description file
Cell name: sky130_fd_sc_ms__dlygate4sd2
Type: cell
Verilog name: sky130_fd_sc_ms__dlygate4sd2
Library: sky130_fd_sc_ms
Inputs: 1 (A)
Outputs: 1 (X)