sky130_fd_sc_ms__a32o¶
3-input AND into first input, and 2-input AND into 2nd input of 2-input OR
This is a stub of cell description file
Cell name: sky130_fd_sc_ms__a32o
Type: cell
Verilog name: sky130_fd_sc_ms__a32o
Library: sky130_fd_sc_ms
Inputs: 5 (A1, A2, A3, B1, B2)
Outputs: 1 (X)