sky130_fd_sc_ls__edfxtp¶
Delay flop with loopback enable, non-inverted clock, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_ls__edfxtp
Type: cell
Verilog name: sky130_fd_sc_ls__edfxtp
Library: sky130_fd_sc_ls
Inputs: 3 (CLK, D, DE)
Outputs: 1 (Q)