sky130_fd_sc_ls__clkdlyinv5sd3

Clock Delay Inverter 5-stage 0.50um length inner stage gate

This is a stub of cell description file

  • Cell name: sky130_fd_sc_ls__clkdlyinv5sd3

  • Type: cell

  • Verilog name: sky130_fd_sc_ls__clkdlyinv5sd3

  • Library: sky130_fd_sc_ls

  • Inputs: 1 (A)

  • Outputs: 1 (Y)

sky130_fd_sc_ls__clkdlyinv5sd3 symbols

../../../../../_images/sky130_fd_sc_ls__clkdlyinv5sd3.symbol.svg
../../../../../_images/sky130_fd_sc_ls__clkdlyinv5sd3.pp.symbol.svg

sky130_fd_sc_ls__clkdlyinv5sd3 schematic

../../../../../_images/sky130_fd_sc_ls__clkdlyinv5sd3.schematic.svg

sky130_fd_sc_ls__clkdlyinv5sd3 GDSII layouts

../../../../../_images/sky130_fd_sc_ls__clkdlyinv5sd3_1.svg

sky130_fd_sc_ls__clkdlyinv5sd3_1