sky130_fd_sc_ls__clkdlyinv5sd2

Clock Delay Inverter 5-stage 0.25um length inner stage gate

This is a stub of cell description file

• Cell name: sky130_fd_sc_ls__clkdlyinv5sd2

• Type: cell

• Verilog name: sky130_fd_sc_ls__clkdlyinv5sd2

• Library: sky130_fd_sc_ls

• Inputs: 1 (A)

• Outputs: 1 (Y)

sky130_fd_sc_ls__clkdlyinv5sd2 symbols

sky130_fd_sc_ls__clkdlyinv5sd2 schematic

sky130_fd_sc_ls__clkdlyinv5sd2 GDSII layouts

sky130_fd_sc_ls__clkdlyinv5sd2_1