sky130_fd_sc_ls__clkdlyinv3sd3¶
Clock Delay Inverter 3-stage 0.50um length inner stage gate
This is a stub of cell description file
Cell name: sky130_fd_sc_ls__clkdlyinv3sd3
Type: cell
Verilog name: sky130_fd_sc_ls__clkdlyinv3sd3
Library: sky130_fd_sc_ls
Inputs: 1 (A)
Outputs: 1 (Y)