sky130_fd_sc_hs__sedfxbp¶
Scan delay flop, data enable, non-inverted clock, complementary outputs
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__sedfxbp
Type: cell
Verilog name: sky130_fd_sc_hs__sedfxbp
Library: sky130_fd_sc_hs
Inputs: 5 (CLK, D, DE, SCD, SCE)
Outputs: 2 (Q, Q_N)