sky130_fd_sc_hs__sdlclkp¶
Scan gated clock
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__sdlclkp
Type: cell
Verilog name: sky130_fd_sc_hs__sdlclkp
Library: sky130_fd_sc_hs
Inputs: 3 (GATE, CLK, SCE)
Outputs: 1 (GCLK)
Scan gated clock
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__sdlclkp
Type: cell
Verilog name: sky130_fd_sc_hs__sdlclkp
Library: sky130_fd_sc_hs
Inputs: 3 (GATE, CLK, SCE)
Outputs: 1 (GCLK)