sky130_fd_sc_hs__sdfxtp¶
Scan delay flop, non-inverted clock, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__sdfxtp
Type: cell
Verilog name: sky130_fd_sc_hs__sdfxtp
Library: sky130_fd_sc_hs
Inputs: 4 (CLK, D, SCD, SCE)
Outputs: 1 (Q)
sky130_fd_sc_hs__sdfxtp symbols¶
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sky130_fd_sc_hs__sdfxtp schematic¶
sky130_fd_sc_hs__sdfxtp GDSII layouts¶
sky130_fd_sc_hs__sdfxtp_1¶
sky130_fd_sc_hs__sdfxtp_2¶
sky130_fd_sc_hs__sdfxtp_4¶