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SkyWater SKY130 PDK sky130_fd_sc_hs__sdfxbp

google/skywater-pdk

sky130_fd_sc_hs__sdfxbp¶

Scan delay flop, non-inverted clock, complementary outputs

This is a stub of cell description file

Cell name: sky130_fd_sc_hs__sdfxbp
Type: cell
Verilog name: sky130_fd_sc_hs__sdfxbp
Library: sky130_fd_sc_hs
Inputs: 4 (CLK, D, SCD, SCE)
Outputs: 2 (Q, Q_N)

sky130_fd_sc_hs__sdfxbp symbols¶

../../../../../_images/sky130_fd_sc_hs__sdfxbp.symbol.svg

../../../../../_images/sky130_fd_sc_hs__sdfxbp.pp.symbol.svg

sky130_fd_sc_hs__sdfxbp schematic¶

contents/libraries/sky130_fd_sc_hs/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp.schematic.svg

sky130_fd_sc_hs__sdfxbp GDSII layouts¶

../../../../../_images/sky130_fd_sc_hs__sdfxbp_1.svg — sky130_fd_sc_hs__sdfxbp_1¶

../../../../../_images/sky130_fd_sc_hs__sdfxbp_2.svg — sky130_fd_sc_hs__sdfxbp_2¶