sky130_fd_sc_hs__sdfstp¶
Scan delay flop, inverted set, non-inverted clock, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__sdfstp
Type: cell
Verilog name: sky130_fd_sc_hs__sdfstp
Library: sky130_fd_sc_hs
Inputs: 5 (CLK, D, SCD, SCE, SET_B)
Outputs: 1 (Q)
sky130_fd_sc_hs__sdfstp symbols¶
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sky130_fd_sc_hs__sdfstp schematic¶
sky130_fd_sc_hs__sdfstp GDSII layouts¶
sky130_fd_sc_hs__sdfstp_1¶
sky130_fd_sc_hs__sdfstp_2¶
sky130_fd_sc_hs__sdfstp_4¶