sky130_fd_sc_hs__fahcin¶
Full adder, inverted carry in
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__fahcin
Type: cell
Verilog name: sky130_fd_sc_hs__fahcin
Library: sky130_fd_sc_hs
Inputs: 3 (A, B, CIN)
Outputs: 2 (COUT, SUM)