sky130_fd_sc_hs__dlymetal6s2s¶
6-inverter delay with output from 2nd stage on horizontal route
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__dlymetal6s2s
Type: cell
Verilog name: sky130_fd_sc_hs__dlymetal6s2s
Library: sky130_fd_sc_hs
Inputs: 1 (A)
Outputs: 1 (X)