sky130_fd_sc_hs__dlxbn¶
Delay latch, inverted enable, complementary outputs
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__dlxbn
Type: cell
Verilog name: sky130_fd_sc_hs__dlxbn
Library: sky130_fd_sc_hs
Inputs: 2 (D, GATE_N)
Outputs: 2 (Q, Q_N)