sky130_fd_sc_hs__dfxtp¶
Delay flop, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__dfxtp
Type: cell
Verilog name: sky130_fd_sc_hs__dfxtp
Library: sky130_fd_sc_hs
Inputs: 2 (CLK, D)
Outputs: 1 (Q)
Delay flop, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__dfxtp
Type: cell
Verilog name: sky130_fd_sc_hs__dfxtp
Library: sky130_fd_sc_hs
Inputs: 2 (CLK, D)
Outputs: 1 (Q)