sky130_fd_sc_hs__dfstp

Delay flop, inverted set, single output

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hs__dfstp

  • Type: cell

  • Verilog name: sky130_fd_sc_hs__dfstp

  • Library: sky130_fd_sc_hs

  • Inputs: 3 (CLK, D, SET_B)

  • Outputs: 1 (Q)

sky130_fd_sc_hs__dfstp symbols

../../../../../_images/sky130_fd_sc_hs__dfstp.symbol.svg
../../../../../_images/sky130_fd_sc_hs__dfstp.pp.symbol.svg

sky130_fd_sc_hs__dfstp schematic

contents/libraries/sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp.schematic.svg

sky130_fd_sc_hs__dfstp GDSII layouts

../../../../../_images/sky130_fd_sc_hs__dfstp_1.svg

sky130_fd_sc_hs__dfstp_1

../../../../../_images/sky130_fd_sc_hs__dfstp_2.svg

sky130_fd_sc_hs__dfstp_2

../../../../../_images/sky130_fd_sc_hs__dfstp_4.svg

sky130_fd_sc_hs__dfstp_4