sky130_fd_sc_hs__dfrtp¶
Delay flop, inverted reset, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__dfrtp
Type: cell
Verilog name: sky130_fd_sc_hs__dfrtp
Library: sky130_fd_sc_hs
Inputs: 3 (RESET_B, CLK, D)
Outputs: 1 (Q)