sky130_fd_sc_hs__dfrtn

Delay flop, inverted reset, inverted clock, complementary outputs

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hs__dfrtn

  • Type: cell

  • Verilog name: sky130_fd_sc_hs__dfrtn

  • Library: sky130_fd_sc_hs

  • Inputs: 3 (RESET_B, CLK_N, D)

  • Outputs: 1 (Q)

sky130_fd_sc_hs__dfrtn symbols

../../../../../_images/sky130_fd_sc_hs__dfrtn.symbol.svg
../../../../../_images/sky130_fd_sc_hs__dfrtn.pp.symbol.svg

sky130_fd_sc_hs__dfrtn schematic

contents/libraries/sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn.schematic.svg

sky130_fd_sc_hs__dfrtn GDSII layouts

../../../../../_images/sky130_fd_sc_hs__dfrtn_1.svg

sky130_fd_sc_hs__dfrtn_1