sky130_fd_sc_hs__dfbbn¶
Delay flop, inverted set, inverted reset, inverted clock, complementary outputs
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__dfbbn
Type: cell
Verilog name: sky130_fd_sc_hs__dfbbn
Library: sky130_fd_sc_hs
Inputs: 4 (D, CLK_N, SET_B, RESET_B)
Outputs: 2 (Q, Q_N)