sky130_fd_sc_hs__and3¶
3-input AND
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__and3
Type: cell
Verilog name: sky130_fd_sc_hs__and3
Library: sky130_fd_sc_hs
Inputs: 3 (A, B, C)
Outputs: 1 (X)
3-input AND
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__and3
Type: cell
Verilog name: sky130_fd_sc_hs__and3
Library: sky130_fd_sc_hs
Inputs: 3 (A, B, C)
Outputs: 1 (X)