sky130_fd_sc_hdll__sdlclkp¶
Scan gated clock
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__sdlclkp
Type: cell
Verilog name: sky130_fd_sc_hdll__sdlclkp
Library: sky130_fd_sc_hdll
Inputs: 3 (SCE, GATE, CLK)
Outputs: 1 (GCLK)
Scan gated clock
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__sdlclkp
Type: cell
Verilog name: sky130_fd_sc_hdll__sdlclkp
Library: sky130_fd_sc_hdll
Inputs: 3 (SCE, GATE, CLK)
Outputs: 1 (GCLK)