sky130_fd_sc_hdll__sdfsbp

Scan delay flop, inverted set, non-inverted clock, complementary outputs

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__sdfsbp

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__sdfsbp

  • Library: sky130_fd_sc_hdll

  • Inputs: 5 (CLK, D, SCD, SCE, SET_B)

  • Outputs: 2 (Q, Q_N)

sky130_fd_sc_hdll__sdfsbp symbols

../../../../../_images/sky130_fd_sc_hdll__sdfsbp.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__sdfsbp.pp.symbol.svg

sky130_fd_sc_hdll__sdfsbp schematic

../../../../../_images/sky130_fd_sc_hdll__sdfsbp.schematic.svg

sky130_fd_sc_hdll__sdfsbp GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__sdfsbp_1.svg

sky130_fd_sc_hdll__sdfsbp_1

../../../../../_images/sky130_fd_sc_hdll__sdfsbp_2.svg

sky130_fd_sc_hdll__sdfsbp_2