sky130_fd_sc_hdll__sdfrtp

Scan delay flop, inverted reset, non-inverted clock, single output

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__sdfrtp

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__sdfrtp

  • Library: sky130_fd_sc_hdll

  • Inputs: 5 (CLK, D, SCD, SCE, RESET_B)

  • Outputs: 1 (Q)

sky130_fd_sc_hdll__sdfrtp symbols

../../../../../_images/sky130_fd_sc_hdll__sdfrtp.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__sdfrtp.pp.symbol.svg

sky130_fd_sc_hdll__sdfrtp schematic

../../../../../_images/sky130_fd_sc_hdll__sdfrtp.schematic.svg

sky130_fd_sc_hdll__sdfrtp GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__sdfrtp_1.svg

sky130_fd_sc_hdll__sdfrtp_1

../../../../../_images/sky130_fd_sc_hdll__sdfrtp_2.svg

sky130_fd_sc_hdll__sdfrtp_2

../../../../../_images/sky130_fd_sc_hdll__sdfrtp_4.svg

sky130_fd_sc_hdll__sdfrtp_4