sky130_fd_sc_hdll__or4bb¶
4-input OR, first two inputs inverted
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__or4bb
Type: cell
Verilog name: sky130_fd_sc_hdll__or4bb
Library: sky130_fd_sc_hdll
Inputs: 4 (A, B, C_N, D_N)
Outputs: 1 (X)