sky130_fd_sc_hdll__o211a

2-input OR into first input of 3-input AND

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__o211a

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__o211a

  • Library: sky130_fd_sc_hdll

  • Inputs: 4 (A1, A2, B1, C1)

  • Outputs: 1 (X)

sky130_fd_sc_hdll__o211a symbols

../../../../../_images/sky130_fd_sc_hdll__o211a.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__o211a.pp.symbol.svg

sky130_fd_sc_hdll__o211a schematic

../../../../../_images/sky130_fd_sc_hdll__o211a.schematic.svg

sky130_fd_sc_hdll__o211a GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__o211a_1.svg

sky130_fd_sc_hdll__o211a_1

../../../../../_images/sky130_fd_sc_hdll__o211a_2.svg

sky130_fd_sc_hdll__o211a_2

../../../../../_images/sky130_fd_sc_hdll__o211a_4.svg

sky130_fd_sc_hdll__o211a_4