sky130_fd_sc_hdll__dlygate4sd3¶
Delay Buffer 4-stage 0.50um length inner stage gates
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__dlygate4sd3
Type: cell
Verilog name: sky130_fd_sc_hdll__dlygate4sd3
Library: sky130_fd_sc_hdll
Inputs: 1 (A)
Outputs: 1 (X)