sky130_fd_sc_hdll__dlrtp¶
Delay latch, inverted reset, non-inverted enable, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__dlrtp
Type: cell
Verilog name: sky130_fd_sc_hdll__dlrtp
Library: sky130_fd_sc_hdll
Inputs: 3 (RESET_B, D, GATE)
Outputs: 1 (Q)