sky130_fd_sc_hdll__dlrtp

Delay latch, inverted reset, non-inverted enable, single output

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__dlrtp

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__dlrtp

  • Library: sky130_fd_sc_hdll

  • Inputs: 3 (RESET_B, D, GATE)

  • Outputs: 1 (Q)

sky130_fd_sc_hdll__dlrtp symbols

../../../../../_images/sky130_fd_sc_hdll__dlrtp.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__dlrtp.pp.symbol.svg

sky130_fd_sc_hdll__dlrtp schematic

../../../../../_images/sky130_fd_sc_hdll__dlrtp.schematic.svg

sky130_fd_sc_hdll__dlrtp GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__dlrtp_1.svg

sky130_fd_sc_hdll__dlrtp_1

../../../../../_images/sky130_fd_sc_hdll__dlrtp_2.svg

sky130_fd_sc_hdll__dlrtp_2

../../../../../_images/sky130_fd_sc_hdll__dlrtp_4.svg

sky130_fd_sc_hdll__dlrtp_4