sky130_fd_sc_hdll__clkinvlp¶
Lower power Clock tree inverter
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__clkinvlp
Type: cell
Verilog name: sky130_fd_sc_hdll__clkinvlp
Library: sky130_fd_sc_hdll
Inputs: 1 (A)
Outputs: 1 (Y)