sky130_fd_sc_hdll__clkbuf¶
Clock tree buffer
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__clkbuf
Type: cell
Verilog name: sky130_fd_sc_hdll__clkbuf
Library: sky130_fd_sc_hdll
Inputs: 1 (A)
Outputs: 1 (X)
Clock tree buffer
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__clkbuf
Type: cell
Verilog name: sky130_fd_sc_hdll__clkbuf
Library: sky130_fd_sc_hdll
Inputs: 1 (A)
Outputs: 1 (X)