sky130_fd_sc_hdll__a2bb2o¶
2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input OR
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__a2bb2o
Type: cell
Verilog name: sky130_fd_sc_hdll__a2bb2o
Library: sky130_fd_sc_hdll
Inputs: 4 (A1_N, A2_N, B1, B2)
Outputs: 1 (X)