sky130_fd_sc_hdll__a21o

2-input AND into first input of 2-input OR

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__a21o

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__a21o

  • Library: sky130_fd_sc_hdll

  • Inputs: 3 (A1, A2, B1)

  • Outputs: 1 (X)

sky130_fd_sc_hdll__a21o symbols

../../../../../_images/sky130_fd_sc_hdll__a21o.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__a21o.pp.symbol.svg

sky130_fd_sc_hdll__a21o schematic

../../../../../_images/sky130_fd_sc_hdll__a21o.schematic.svg

sky130_fd_sc_hdll__a21o GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__a21o_1.svg

sky130_fd_sc_hdll__a21o_1

../../../../../_images/sky130_fd_sc_hdll__a21o_2.svg

sky130_fd_sc_hdll__a21o_2

../../../../../_images/sky130_fd_sc_hdll__a21o_4.svg

sky130_fd_sc_hdll__a21o_4

../../../../../_images/sky130_fd_sc_hdll__a21o_6.svg

sky130_fd_sc_hdll__a21o_6

../../../../../_images/sky130_fd_sc_hdll__a21o_8.svg

sky130_fd_sc_hdll__a21o_8