sky130_fd_sc_hd__sdfrtn¶
Scan delay flop, inverted reset, inverted clock, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_hd__sdfrtn
Type: cell
Verilog name: sky130_fd_sc_hd__sdfrtn
Library: sky130_fd_sc_hd
Inputs: 5 (CLK_N, D, SCD, SCE, RESET_B)
Outputs: 1 (Q)