sky130_fd_sc_hd__sdfbbp¶
Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs
This is a stub of cell description file
Cell name: sky130_fd_sc_hd__sdfbbp
Type: cell
Verilog name: sky130_fd_sc_hd__sdfbbp
Library: sky130_fd_sc_hd
Inputs: 6 (D, SCD, SCE, CLK, SET_B, RESET_B)
Outputs: 2 (Q, Q_N)
sky130_fd_sc_hd__sdfbbp symbols¶
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sky130_fd_sc_hd__sdfbbp schematic¶
sky130_fd_sc_hd__sdfbbp GDSII layouts¶
sky130_fd_sc_hd__sdfbbp_1¶