sky130_fd_sc_hd__edfxbp¶
Delay flop with loopback enable, non-inverted clock, complementary outputs
This is a stub of cell description file
Cell name: sky130_fd_sc_hd__edfxbp
Type: cell
Verilog name: sky130_fd_sc_hd__edfxbp
Library: sky130_fd_sc_hd
Inputs: 3 (CLK, D, DE)
Outputs: 2 (Q, Q_N)