sky130_fd_sc_hd__dlxtp

Delay latch, non-inverted enable, single output

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hd__dlxtp

  • Type: cell

  • Verilog name: sky130_fd_sc_hd__dlxtp

  • Library: sky130_fd_sc_hd

  • Inputs: 2 (D, GATE)

  • Outputs: 1 (Q)

sky130_fd_sc_hd__dlxtp symbols

../../../../../_images/sky130_fd_sc_hd__dlxtp.symbol.svg
../../../../../_images/sky130_fd_sc_hd__dlxtp.pp.symbol.svg

sky130_fd_sc_hd__dlxtp schematic

../../../../../_images/sky130_fd_sc_hd__dlxtp.schematic.svg

sky130_fd_sc_hd__dlxtp GDSII layouts

../../../../../_images/sky130_fd_sc_hd__dlxtp_1.svg

sky130_fd_sc_hd__dlxtp_1