sky130_fd_sc_hd__dlrtn

Delay latch, inverted reset, inverted enable, single output

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hd__dlrtn

  • Type: cell

  • Verilog name: sky130_fd_sc_hd__dlrtn

  • Library: sky130_fd_sc_hd

  • Inputs: 3 (RESET_B, D, GATE_N)

  • Outputs: 1 (Q)

sky130_fd_sc_hd__dlrtn symbols

../../../../../_images/sky130_fd_sc_hd__dlrtn.symbol.svg
../../../../../_images/sky130_fd_sc_hd__dlrtn.pp.symbol.svg

sky130_fd_sc_hd__dlrtn schematic

../../../../../_images/sky130_fd_sc_hd__dlrtn.schematic.svg

sky130_fd_sc_hd__dlrtn GDSII layouts

../../../../../_images/sky130_fd_sc_hd__dlrtn_1.svg

sky130_fd_sc_hd__dlrtn_1

../../../../../_images/sky130_fd_sc_hd__dlrtn_2.svg

sky130_fd_sc_hd__dlrtn_2

../../../../../_images/sky130_fd_sc_hd__dlrtn_4.svg

sky130_fd_sc_hd__dlrtn_4