sky130_fd_sc_hd__dfxtp

Delay flop, single output

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hd__dfxtp

  • Type: cell

  • Verilog name: sky130_fd_sc_hd__dfxtp

  • Library: sky130_fd_sc_hd

  • Inputs: 2 (CLK, D)

  • Outputs: 1 (Q)

sky130_fd_sc_hd__dfxtp symbols

../../../../../_images/sky130_fd_sc_hd__dfxtp.symbol.svg
../../../../../_images/sky130_fd_sc_hd__dfxtp.pp.symbol.svg

sky130_fd_sc_hd__dfxtp schematic

../../../../../_images/sky130_fd_sc_hd__dfxtp.schematic.svg

sky130_fd_sc_hd__dfxtp GDSII layouts

../../../../../_images/sky130_fd_sc_hd__dfxtp_1.svg

sky130_fd_sc_hd__dfxtp_1

../../../../../_images/sky130_fd_sc_hd__dfxtp_2.svg

sky130_fd_sc_hd__dfxtp_2

../../../../../_images/sky130_fd_sc_hd__dfxtp_4.svg

sky130_fd_sc_hd__dfxtp_4