sky130_fd_sc_hd__clkdlybuf4s50

Clock Delay Buffer 4-stage 0.59um length inner stage gates

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hd__clkdlybuf4s50

  • Type: cell

  • Verilog name: sky130_fd_sc_hd__clkdlybuf4s50

  • Library: sky130_fd_sc_hd

  • Inputs: 1 (A)

  • Outputs: 1 (X)

sky130_fd_sc_hd__clkdlybuf4s50 symbols

../../../../../_images/sky130_fd_sc_hd__clkdlybuf4s50.symbol.svg
../../../../../_images/sky130_fd_sc_hd__clkdlybuf4s50.pp.symbol.svg

sky130_fd_sc_hd__clkdlybuf4s50 schematic

../../../../../_images/sky130_fd_sc_hd__clkdlybuf4s50.schematic.svg

sky130_fd_sc_hd__clkdlybuf4s50 GDSII layouts

../../../../../_images/sky130_fd_sc_hd__clkdlybuf4s50_1.svg

sky130_fd_sc_hd__clkdlybuf4s50_1

../../../../../_images/sky130_fd_sc_hd__clkdlybuf4s50_2.svg

sky130_fd_sc_hd__clkdlybuf4s50_2